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AX88875AP 数据表(PDF) 8 Page - ASIX Electronics Corporation

部件名 AX88875AP
功能描述  10/100BASE 5-Port Dual Speed Bripeater Controller
PDF  23 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88875AP 数据表(HTML) 8 Page - ASIX Electronics Corporation

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AX88875AP Bripeater
ASIX ELECTRONICS CORPORATION
8
2.0 Pin Description
The following terms describe the AX88875A pinout:
All pin names with the “/” suffix are asserted low.
I
=
Input
O
=
Output
I/O
=
Input /Output
2.1 MII interfaces
Signal Name
Type
Pin No.
Description
TXER[4:0]
Or
COL[4:0]
O
or
I
66, 44, 28
9, 154
Transmit Error : When /HALF10 pin set to “high”. TXER is transition
synchronously with respect to the rising edge of TXCLK . Asserted
high when a code violation is request to be send
Collision : When /HALF10 pin set to “low”. COL is input from PHY,
when 10Mbps PHY is in half-duplex mode.
TXD[4:0][3:0]
O
65 – 62, 43 – 40
27 – 24, 8 – 5
153 - 150
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TXCLK. For each TXCLK period in which TXEN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
TXEN[4:0]
O
61, 39, 23
4, 149
Transmit Enable : TXEN is transition synchronously with respect to the
rising edge of TXCLK. TXEN indicates that the port is presenting
nibbles on TXD [3:0] for transmission.
RXD[4:0][3:0]
I
60 – 57, 37 – 34
22 – 19, 3, 2
160, 159,
147 - 144
Receive Data : RXD [3:0] is driven by the PHY synchronously with
respect to RXCLK.
RXER[4:0]
I
51, 30, 15,
155, 140
Receive Error : RXER ,is driven by PHY and synchronous to RXCLK,
is asserted for one or more RXCLK periods to indicate to the port that
an error has detected.
RXCLK[4:0]
I
56, 33,
18, 158, 143
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RXDV,RXD [3:0] and RXER
signals from the PHY to the MII port of the repeater.
RXDV[4:0]
I
52, 31,
16, 156, 141
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RXCLK. Asserted high when valid data is present on RXD
[3:0].
CRS[4:0]
I
53, 32,
17, 157, 142
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when
receive medium is non-idle at full duplex mode.
COL_O[4]
O
67
Collision : Collision detection signal for port 4



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