Preliminary datasheet
21
Version: DM9102D-DS-P02
Jan. 14, 2005
6.2 Control and Status Registers (CR)
The DM9102D implements 16 control and status registers,
which can be accessed by the host. These CRs are double
long word aligned. All CRs are set to their default values by
hardware or software reset unless otherwise specified. All
Control and Status Registers with their definitions and offset
from IO or memory Base Address are shown below:
Register
Description
Offset from CSR
Base Address
Default value
after reset
CR0
System Control Register
00H
DE000000H
CR1
Transmit Descriptor Poll Demand
08H
FFFFFFFFH
CR2
Receive Descriptor Poll Demand
10H
FFFFFFFFH
CR3
Receive Descriptor Base Address Register
18H
00000000H
CR4
Transmit Descriptor Base Address Register
20H
00000000H
CR5
Network Status Report Register
28H
FC000000H
CR6
Network Operation Mode Register
30H
02040000H
CR7
Interrupt Mask Register
38H
FFFE0000H
CR8
Statistical Counter Register
40H
00000000H
CR9
External Management Access Register
48H
000083F0H
CR10
Reserved
50H
FFFFFFFFH
CR11
Reserved
58H
FFFE0000H
CR12
PHY Status Register
60H
FFFFFFXXH
CR13
Sample Frame Access Register
68H
XXXXXX00H
CR14
Sample Frame Data Register
70H
Unpredictable
CR15
Watchdog And Jabber Timer Register
78H
00000000H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
RW/C = Read/Write and Clear
WO = Write only
RO/C = Read only and cleared after read.
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
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