October 1995

1/8

ST 486 DX ASIC CORE

Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE

PRELIMINARY DATA

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Fully Static 486 compatible core able to

operate from D.C to 120MHz

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Manufactured in a 0.35 micron five layer

metal HCMOS process

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8K byte unified instruction and data cache

with write back capability

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Parallel processing integral floating point unit,

with automatic power down mode

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Low Power system management modes

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Cell libraries for 2.2V and 3.3V supply with

5 V I/O interface capability

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2 - input NAND delay of 0.160 ns (typ) with

fanout = 2.

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Broad I/O functionality including LVCMOS,

LVTTL, GTL, PECL, and LVDS.

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High drive I/O; capability of sinking up to 48

mA with slew rate control, current spike sup-

pression and impedance matching.

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Generators to support SPRAM, DPRAM,

ROM and many other embedded functions.

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Fully independent power and ground configu-

rations for inputs, core and outputs.

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Programmable I/O ring capability up to 1000

pads.

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Output buffers capable of driving ISA, EISA,

PCI, MCA, and SCSI interface levels.

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Active pull up and pull down devices.

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Buskeeper I/O functions.

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Oscillators for wide frequency spectrum.

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Broad range of 400 SSI cells.

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Design For Test includes LSSD macro library

option and IEEE 1149.1 JTAG Boundary

Scan architecture built in.

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Cadence based design system with inter-

faces from multiple workstations.

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Broad ceramic and plastic package range.

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Latchup trigger current > +/- 500 mA.

ESD protection > +/- 4000 volts.

Se a o f G at e s

S t a n d ar d C e lls

C u s t o m I/ O

Pr o g ra m m a b le

I/O

e .g RAM DAC

SV G A

CHIP S E T / P C I

ID E / IS A

48 6 D X C O R E

RO M

RAM

DP RAM

Figure 1. Example 486 DX Core ASIC