ST 486 DX ASIC CORE

4/8

®

Examples include mixed mode cells for graphics,

DAC/ADC’s (4-9 bit), PLL applications, and Digital

Signal Processor functions for cellular comms, fax

and

high-speed

modem.

100

Mbps

serial

transputer links coupled with large and fast

memory can be used for pipelining, caching and

synchro

circuits in

modern

CISC

computing

architecture.

Viterbi and Reed Solomon cores aim at the HDTV

and satellite transmission markets. To support

telecom needs for CCITT standard applications,

ADPCM cells supporting CT2 protocol have been

developed. MPEG2 decoders interfacing directly

to the system memory are ideal for settop and

cable applications.

DESIGN FOR TESTABILITY

Using the internal test modes of the 486 core,

accessed through special test logic, the core

module can be thoroughly tested in ‘stand alone’

mode at both wafer sort and packaged die test.

The

HCMOS

6

library

supports

the

JTAG

boundary Scan and both edge and level sensitive

scan

design

techniques

by

providing

the

necessary macrocells. Scan testing aids device

testability by permitting access to internal nodes

without requiring a separate external connection

for each node accessed. Testability is assured at

device level with the close coupling of LSSD latch

elements, Automatic Test Pattern Generation

(ATPG) and high pattern depth tester architecture.

At system level, SGS-THOMSON fully supports

IEEE 1149.1. Several types of core scan cells are

provided in the HCMOS 6 library.

PACKAGE AVAILABILITY

The HCMOS 6 library is designed to be compatible

with QFP and BGA package types, in addition to

the more traditional types of package.

The options include Quad Flat Pack (xQFP)

offering ranges up to 304 pins.

Both high

performance and high power variants are available

as well as the TQFP thin types.

Ball Grid Array (BGA) packages are available from

160 to 500 pins.

Pin counts for through board mounting range up to

299. For higher pin counts the range is compatible

with the industry standard JEDEC and EIA-J

Guardring Quad Flatpack (GQPF) with pin counts

from 186 to 304.

The diversity in pin count and package style gives

the designer the opportunity to find the best

compromise

for

system

size,

cost

and

performance requirements.

DESIGN ENVIRONMENT

Several interface levels are possible between

SGS-THOMSON

and

the

customer

in

the

undertaking of a 486 Core design. The four levels

of interface are shown in Figure 3. Level 1 is

characterized by SGS-THOMSON receiving the

system specification and taking the design through

to validation and fabrication. At level 2 interface

the designer supplies a simulated netlist at the

RTL HDL level. SGS-THOMSON then takes the

design through synthesis and gate level simulation

to layout, validation and fabrication.

Level 3 the designer completes the design to final

gate level simulation. The design is then taken

through layout, validation and fabrication by SGS-

THOMSON.

At level 4 the designer completes all of the design

and layout and supplies the design database to

SGS-THOMSON

in

GDS

2

format.

SGS-

THOMSON will then complete LVS and DRC and

generate the PG tape for mask generation and

fabrication.

TECHNOLOGY

For this product, a high performance, low voltage,

five level metal, salicided poly and diffusion

HCMOS 0.35 micron process has been used to

achieve sub-nanosecond internal speeds while

offering very low power dissipation and high noise

immunity.

Its fabrication involve more than 140 elementary

operations,

including

selective

tungsten vias,

plasma interment dielectric deposition and CMP

(Chemical-Mechanical

Planarization)

for

the

incrementally oxides.

METHODOLOGY

The

design

environment

for

x86

embedded

products

has

been

designed

for

maximum

flexibility and reliability, and has been based on

typical ASIC like design flows using HDL and

Synthesis methodologies.