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IXYS reserves the right to change limits, test conditions and dimensions

General Informations for Chips

When mounting Power Semiconductor chips to a header, ceramic substrate or hybrid thick film circuit, the solder system and the chip

attach process are very important to the reliability and performance of the final product. This brochure provides several guidelines

that describe recommended chip attachment pro-cedures. These methods have been used successfully for many years at IXYS.

Available forms of chip packings

IXYS offers various options.

Please order from one of the following possibilities:

Packaging Options

Delivery form

C-...*

Chips in tray (Waffle Pack);

Electrically tested

T-...*

Chips in wafer, unsawed;

Bipolar = 5" (125 mm

∅) wafer; Electrically tested, rejects are inked

W-...*

Chips in wafer on foil, sawed;

Bipolar = 5" (125 mm

∅) wafer; Electrically tested, rejects are inked

...* must be amended by the exact chip type designation.

Packing, Storage and Handling

Chips should be transported in their original containers. All chip transfer to other containers or for assembly should be done only with

rubber-tipped vacuum pencils. Contact with human skin (or with a tool that has been touched by hand) leaves an oily residue that may

adversely impact subsequent chip attach or reliability.

At temperatures below 104

°F (40°C), there is no limitation on storage time for chips in sealed original packages. Chips removed from

original packages should be assembled immediately. The wetting ability of the contact metallization with solder can be preserved by

storage in a clean and dry nitrogen atmosphere.

The IGBT and MOSFET Chips are electrostatic discharge (ESD) sensitive. Normal ESD precautions for handling must be observed.

Prior to chip attach, all testing and handling of the chips must be done at ESD safe work stations according to DIN IEC 47(CO) 701.

Ionized air blowers are recommended for added ESD protection.

Contamination of the chips degrades the assembly results.Finger prints, dust or oily deposits on the surface of the chips have to be

absolutely avoided.

Rough mechanical treatment can cause damage to the chip.

Electrical Tests

The electrical properties listed in the data sheet presume correctly assembled chips. Testing of non-assembled chips requires the

following precautions:

- High currents have to be supplied homogeneously to the whole metallized contact area.

- Kelvin probes must be used to test voltages at high currents

- Applying the full specified blocking or reverse voltage may cause arcing across the glass passivated junction termination, because

the electrical field on top of the passivation glass causes ionization of the surrounding air. This phenomenon can be avoided by using

inert fluids or by increasing the pressure of the gas surrounding the chip to values above 30 psig (2 bars).

General Rules for Assembly

The linear thermal expansion coefficient of silicon is very small compared to usual contact metals. If a large area metallized silicon

chip is directly soldered to a metal like copper, enormous shear stress is caused by temperature changes (e.g. when cooling down from

the solder temperature or by heating during working conditions) which can disrupt the solder mountdown.

If it is found that larger chips are cracking during mountdown or in the application, then the use of a low thermal expansion coefficient

larger chips to DCB ceramic substrates because of their matching thermal expansion coefficients.

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