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TMX320C6201GFN167 数据表(PDF) 21 Page - Texas Instruments |
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TMX320C6201GFN167 数据表(HTML) 21 Page - Texas Instruments |
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21 / 83 page  TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 § PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. ¶ A = Analog signal (PLL Filter) # The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ resistor. Terminal Functions (Continued) SIGNAL TYPE† IPD/ DESCRIPTION NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15 B14 IPU HD14 C14 IPU HD13 A15 IPU HD12 C15 IPU HD11 A16 IPU Host-port data U d f t f f d t dd d t l HD10 B16 IPU • Used for transfer of data, address, and control • Also controls initialization of DSP modes at reset via pullup/pulldown resistors HD9 C16 IPU • Also controls initialization of DSP modes at reset via pullup/pulldown resistors − Device Endian mode HD8 B17 I/O/Z IPU Device Endian mode HD8: 0 – Big Endian 1 Little Endian HD7 A18 I/O/Z IPU 1 − Little Endian − Boot mode HD6 C17 IPU − Boot mode HD[4:3]: 00 – HPI boot HD5 B18 IPU HD[4:3]: 00 HPI boot 01 − 8-bit ROM boot with default timings 10 16 bit ROM boot with default timings HD4 C19 IPD 10 − 16-bit ROM boot with default timings 11 − 32-bit ROM boot with default timings HD3 C20 IPU 11 − 32-bit ROM boot with default timings HD2 D18 IPU HD1 D20 IPU HD0 E20 IPU HAS E18 I IPU Host address strobe HCS F20 I IPU Host chip select HDS1 E19 I IPU Host data strobe 1 HDS2 F18 I IPU Host data strobe 2 HRDY H19 O IPD Host ready (from DSP to host) EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 V6 O/Z IPU CE2 W6 O/Z IPU Memory space enables • Enabled by bits 28 through 31 of the word address CE1 W18 O/Z IPU • Enabled by bits 28 through 31 of the word address • Only one asserted during any external data access CE0 V17 O/Z IPU • Only one asserted during any external data access BE3 V5 O/Z IPU Byte-enable control BE2 Y4 O/Z IPU Byte-enable control • Decoded from the two lowest bits of the internal address BE1 U19 O/Z IPU • Decoded from the two lowest bits of the internal address • Byte-write enables for most types of memory C b di tl t d t SDRAM d d it k i l (SDQM) BE0 V20 O/Z IPU yyp y • Can be directly connected to SDRAM read and write mask signal (SDQM) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) |
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