USBLC6-2

4/11

TECHNICAL INFORMATION

1. SURGE PROTECTION

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.

We assume that the value of the dynamic resistance of the clamping diode is typically:

So, we find:

Note: the calculations do not take into account phenomena due to parasitic inductances.

2. SURGE PROTECTION APPLICATION EXAMPLE

two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks

are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the

The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping

voltage will be :

We can reduce as much as possible these phenomena with simple layout optimization.

It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good

ESD protection”).

Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout

Lw

VI/O

ESD

SURGE

GND

I/O

Lw di

dt

Lw di

dt

V+ =

CL

V

+V +Lw

BUS

F

di

dt

surge >0

di

dt

surge <0

V- =

CL

-V -Lw

F

t

tr=1ns

VV

CC

F

+

Lw

di

dt

POSITIVE

SURGE

183V

-Lw

di

dt

t

tr=1ns

-

NEGATIVE

SURGE

-178V