CS5397 datasheet(13/40 Pages) CIRRUS

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CS5396 CS5397

DS229PP2

mats. The serial data interface is accomplished via

the serial data outputs; SDATA1 and SDATA2; se-

rial data clock, SCLK, and the left/right clock,

LRCK. The serial nature of the output data results

in the left and right data words being read at differ-

ent times. However, the samples within an LRCK

cycle represent simultaneously sampled analog in-

puts.

Serial Data- Stand-Alone Mode

The serial data block consists of 24 bits of audio

data presented in 2’s-complement format with the

MSB-first. The data is clocked from SDATA1 and

SDATA2 by the serial clock and the channel is de-

termined by the Left/Right clock. The full precision

24-bit data is available on SDATA1 and the output

from the low group delay filter is available on

SDATA2.

Serial Clock - Stand-Alone Mode

The serial clock shifts the digitized audio data from

the internal data registers via the SDATA1 and

SDATA2 pins. SCLK is an output in Master Mode

where internal dividers will divide the master clock

by 4 to generate a serial clock which is 64

× Fs. In

Slave Mode, SCLK is an input with a serial clock

typically between 48

× and 128× Fs. However, it is

recommended that SCLK be equal to 64

×, though

other frequencies are possible, to avoid potential

interference effects which may degrade system per-

formance.

Left/Right Clock - Stand-Alone Mode

The Left/Right clock, LRCK, determines which

channel, left or right, is to be output on SDATA1

and SDATA2. In Master Mode, LRCK is an output

whose frequency is equal to Fs. In Slave Mode,

LRCK is an input whose frequency must be equal

to Fs and synchronous to MCLKA/D.

Master Mode - Stand-Alone Mode

In Master mode, SCLK and LRCK are outputs

which are internally derived from the master clock.

Internal dividers will divide MCLKA/D by 4 to

generate a SCLK which is 64

× Fs and by 256 to

generate a LRCK which is equal to Fs. The

CS5396/97 is placed in the Master mode with the

slave/master pin, S/M, low.

Slave Mode - Stand-Alone Mode

LRCK and SCLK become inputs in SLAVE mode.

LRCK must be externally derived from MCLKA/D

and be equal to Fs. It is recommended that SCLK

be equal to 64

×. Other frequencies between 48×

and 128

× Fs are possible but may degrade system

performance due to interference effects. The mas-

ter clock frequency must be 256

× Fs. The

CS5396/97 is placed in the Slave mode with the

slave/master pin, S/M, high.

High Pass Filter - Stand-Alone Mode

The CS5396/97 includes a high pass filter after the

decimator to remove the DC offsets introduced by

the analog buffer stage and the CS5396/97 analog

modulator. The characteristics of this first-order

high pass filter are outlined below, for Fs equal to

48 kHz. This filter response scales linearly with

sample rate.

Frequency response: -3 dB @ 1.8 Hz

-0.036 dB @ 20 Hz

Phase deviation:

5.3 degrees @ 20 Hz

Passband ripple:

None

Power-up and Calibration - Stand-Alone

Mode

The delta-sigma modulators settle in a matter of

microseconds after the analog section is powered,

either through the application of power or by exit-

ing the power-down mode. However, the voltage

reference will take a much longer time to reach a fi-

nal value due to the presence of external capaci-

tance on the VREF pin. A time delay of

approximately 10ms/

µF is required after applying

power to the device or after exiting a power down

state.

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