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Notice: The information in this document is subject to change without notice

5V µP Power Supply Monitor and Reset Circuit

ASM1232LP/LPS

January 2005

rev 1.5

resets become active and remain active for a minimum time

period of 250ms after PBRST returns HIGH.

The debounced input is guaranteed to recognize pulses

greater than 20ms. No external pull-up resistor is required,

since PBRST is pulled HIGH by an internal 40k

Ω resistor.

The PBRST can be driven from a TTL or CMOS logic line or

shorted to ground with a mechanical switch.

Watchdog Timer and ST Input

A watchdog timer stops and restarts a microprocessor that is

“hung-up”. The µP must toggle the ST input within a set

period (as selectable through TD input) to verify proper

software execution. If the ST is not toggled low within the

minimum timeout period, reset signals become active. In

power-up after the supply voltage returns to an in-tolerance

condition, the reset signal remains active for 250ms

minimum,

allowing

the

power

supply

and

system

microprocessor to stabilize. ST pulses as short as 20ns can

be detected.

Timeouts periods of approximately 150ms, 610ms or

1,200ms are selected through the TD pin.

The watchdog timer can not be disabled. It must be strobed

with a high-to-low transition to avoid watchdog timeout and

reset.

TD Voltage level

Watchdog Time-out Period

(ms)

Min

Nom

Max

GND

62.5

150

250

Floating

250

610

1000

500

1200

2000

RESET

RESET

PBRST

Figure 3: Timing Diagram: Pushbutton Reset

PBRST

TD

TOL

GND

ST

RESET

RESET

1

2

3

4

5

6

7

8

µP

RESET

5V

ASM1232LP/LPS

Figure 4: Application Circuit: Pushbutton Reset

Valid

Valid

Invalid

ST

RESET

Strobe

Strobe

Strobe

Figure 5: Timing Diagram: Strobe Input

Note: ST is ignored whenever a reset is active

PBRST

TOL

GND

ST

RESET

1

2

3

4

5

6

7

8

µP

RESET

5V

ASM1232 LP/LPS

Figure 6: Application Circuit: Watchdog Timer

Decoder

Address

Bus

MREQ

10kΩ

I/O