UCA9617L-SM2-R datasheet(8/8 Pages) UTC

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UCA9617

Preliminary

CMOS IC

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QW-R140-017.a

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TYPICAL APPLICATION CIRCUIT

The UCA9617 is 5V tolerant, so it does not require any additional circuitry to translate between 0.8V to 5.5V bus

voltages and 2.2V to 5.5V bus voltages. A typical application is shown in Figure 7. In this example, the system master

is running on a 3.3V I

2C-bus while the slave is connected to a 1.2V bus. Both buses run at 1000kHz. Master devices

ca n be placed on either bus.

When port A of the UCA9617 is pulled LOW by a driver on the I

2C-bus, a comparator detects the falling edge when

it goes below 0.3VCC(A) and causes the internal driver on port B to turn on, causing port B to pull down to about 0.5V.

When port B of the UCA9617 falls, first a CMOS hysteresis type input detects the falling edge and causes the internal

driver on port A to turn on and pull the port A pin down to ground.

The VCC(A) is only used to provide the 0.35VCC(A) reference to the port A input comparators and for the power good

detect circuit. The UCA9617 includes a VCC(A) overvoltage disable that turns the channel off if

0.4VCC(A)+0.8V>VCC(B). The UCA9617 logic and all I/Os are powered by the VCC(B) pin.

Figure 7. Typical application

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