Features

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Embedded ICE (In-Circuit Emulation)

– 128-kByte Program and Data RAM

– 16-bit Fixed-point Digital Signal Processing Core

– High-performance Dual MAC Architecture

– 75 MHz Single Clock Design

– Fully Integrated, Supports all DAB Functions and

Modes

– Full Data Rate of 1.8 Mbit Can Be Decoded

– Proven Time and Frequency Synchronization

with a Wide-range Parameter Set

– Automatic Mode Detection (AMD)

– Digital AFC (Frequency Tolerance < 0.5 Hz for Mode I)

– Digital AGC with a Wide Gain Control Range

– Demodulation and Decoding of up to 64 UEP/EEP Sub-channels

– Support of Dynamic Multiplex Reconfiguration (DMR) without Mute State

– Digital Zero-symbol Detection (FSYNCH Generation)

– On-chip De-interleaver Memory for Full 1.8 Mbit/s Decoding Data Rate

– Programmable Fader

– Programmable DRC

– PAD Extraction

– Two Independent Data Packet Mode Decoder

– Supports Wide IF Range of 2.048 MHz to 50 MHz

– Complex Bandpass Filtering

– Optional SAW Filter Equalization

– Audio Player MPEG3 Support

– I2S/SPDIF, SFCO, SSO, RDI, RS-232, USART

– USB 2.0 Full Speed

– Two USARTs

– CAN 2.0A and 2.0B

– Two Dedicated Peripheral Data Controller (PDC) Channels

– 8- to 16-bit Programmable Data Length

– Four External Slave Chip Selects

– CPU and Peripherals Can Be De-activated Individually

– Simple But Comfortable Gearing and Clocking Unit

Electrostatic sensitive device.

Observe precautions for handling.

DAB Digital

Processing

Device

ATR2740

Summary

Preliminary

Note: This is a summary document. A complete document

is available under NDA. For more information, please con-

tact your local Atmel sales office

Rev. 4816BS–DAB–11/04