PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

AD5380

–13–

power-on values. This sequence takes 300us (typ). The falling edge of

RESET initiates the

RESET process and

BUSY goes low for the duration returning high when RESET is

complete.

While BUSY is low all interfaces are disabled and all LDAC pulses are ignored.

When BUSY returns high the part resumes normal operation and the status of the RESET

pin is ignored till the next falling edge is detected.

P D

Power Down (level sensitive active high). Used to place the device in low power mode where

the device consumes less than 5uA. In power pown mode all internal analog circuitry is

placed in low power mode, the analog output will be configured as high impedance outputs

or will provide a 100k load to ground depending on how the power down mode is

configured. The serial interface remains active during power down.

FIFO_EN

FIFO Enable (level sensitive active high). When connected to DVCC the internal FIFO is

enabled allowing the user to write to the device at full speed. FIFO is only available in

parallel interface mode. The status of the FIFO_EN pin is sampled on power-up, and also

following a CLEAR or RESET to determine if the FIFO is enabled. In either serial or I2C

interface modes the FIFO_EN pin shpould be tied low.

DB11 (SPI/

I2C)

Multi-function input pin. In parallel interface mode this pin acts as DB11 of the parallel

input data word. In serial interface mode this pin acts as serial interface mode select.

When serial interface mode is selected (SER/

PAR =1) and this input is low I2C Mode is

selected. In this mode DB12 is the serial clock

(SCLK) input and DB13 is the serial data

(DIN) input.

When serial interface mode is selected (SER/

PAR =1) and this input is high SPI Mode is

selected. In this mode DB12 is the serial clock (SCL) input and DB13 is the serial data

(SDA) input.

DB12 (SCLK/SCL)

Multi-function input pin. In parallel interface mode this pin acts as DB12 of the parallel

input data word. In serial interface mode this pin acts as a serial clock input.

Serial Interface Mode: In serial interface mode data is clocked into the shift register on the

falling edge of SCLK. This operates at clock speeds up to 50 MHz.

I2C Mode: In I2C mode this pin performs the SCL function, clocking data into the device.

Data transfer rate in I2C mode is compatible with both 100kHz and 400kHz operating

modes.

DB13/(DIN/SDA)

Multi-function data input pin.

In parallel interface mode this pin acts as DB13 of the parallel input data word.

Serial Interface Mode: In serial interface mode this pin acts as the serial data input. Data

must be valid on the falling edge of SCLK.

I2C Mode: In I2C mode this pin is the serial Data pin (SDA) operating as an open drain

input/output.