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AD1837AASZ 数据表(PDF) 21 Page - Analog Devices

部件名 AD1837AASZ
功能描述  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD1837AASZ 数据表(HTML) 21 Page - Analog Devices

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REV. A
AD1837A
–21–
Table IX. ADC Peak
Function
Four
Address
R/
W RES Six Data Bits
Fixed Bits
15, 14, 13, 12
11
10
9, 8, 7, 6, 5, 4
3, 2, 1, 0
1010 = Left ADC
1
0
000000 = 0 dBFS
0000
1011 = Right ADC
000001 = –1 dBFS
000010 = –2 dBFS
These
four bits
are always
zero.
111111 = –63 dBFS
Table X. ADC Control 1
Function
ADC
Sample
Address
R/
W
RES
Reserved
Filter
Power-Down
Rate
Reserved
15, 14, 13, 12
11
10
9
8
7
6
5, 4, 3, 2, 1, 0
1100
0
0
0
0 = All Pass
0 = Normal
0 = 48 kHz
0, 0, 0, 0, 0, 0
1 = High-Pass
1 = Power-Down
1 = 96 kHz
0, 0, 0, 0, 0, 0
Table XI. ADC Control 2
Function
R/
W
Master/Slave
ADC
ADC Data-
ADC MUTE
Address
RES
RES
Aux Mode
Data Format
Word Width
Reserved
Right
Left
15, 14, 13, 12
11
10
9
8, 7, 6
5, 4
3, 2
1
0
1101
0
0
0 = Slave
000 = I
2S
00 = 24 Bits
0, 0
0 = On
0 = On
1 = Master
001 = RJ
01 = 20 Bits
1 = Mute
1 = Mute
010 = DSP
10 = 16 Bits
011 = LJ
11 = Reserved
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
Table XII. ADC Control 3
Function
R/
W
IMCLK
ADC
DAC
ADC
Address
RES
RES
Reserved
Clocking Scaling
Peak Readback
Test Mode
Test Mode
15, 14,
13, 12
11
10
9, 8
7, 6
5
4, 3, 2
1, 0
1110
0
0
0, 0
00 = MCLK
20 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
01 = MCLK
1 = Enabled Peak Readback
All others reserved
All others reserved
10 = MCLK
2/3
11 = MCLK
2
Table VIII. DAC Volume Control
Function
Address
R/
W
RES
DAC Volume
15, 14, 13, 12
11
10
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
0010 = DACL1
0
0
0000000000 = Mute
0011 = DACR1
0000000001 = 1/1023
0100 = DACL2
0000000010 = 2/1023
0101 = DACR2
1111111110 = 1022/1023
0110 = DACL3
1111111111 = 1023/1023
0111 = DACR3
1000 = DACL4
1001 = DACR4



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