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ATSAM3103

6093A–DRMSD–25-Oct-04

DSP Array Block

Diagram

Figure 1. ATSAM3103 DSP Array Block Diagram

Functional Description

DSP Array

The ATSAM3103 includes three on-chip DSPs.

Each DSP (P24) is built around a 2K x 24 RAM and a 1K x 24 ROM. The RAM contains

both data and P24 instructions; the ROM contains typical coefficients such as FFT

cosines and windowing. A P24 sends and receives audio samples through the Sync

Bus. It can request external data such as compressed audio through the Async Bus.

Each P24 RAM can be accessed through the Async Bus.

Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse

and butterfly (multiplication of complex numbers). It also includes specialized audio

instructions such as state variable IIR filtering, envelope generation, linear interpolation

and wavetable loop.

One P24 is sufficient for processing one channel of MP3, implementing a multi-tap delay

line or a multi-tap transversal filter. A single P24 is also capable of generating 12 voices

of wavetable sound at 32 kHz sampling rate (8 voices at 48 kHz), including sample

cache, pitch control, second-order filter and two envelope generators.

Sync Bus

The Sync Bus transfers data on a frame basis, typical frame rates being 32, 44.1, 48 or

96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles.

Each P24 is assigned a hardwired time slot (8 to 63), during which it may provide 24-bit

data to the bus (up to 4 data samples). Each P24 can read data on the bus at any time,

MMU

16-bit

Processor

(P16)

Embedded

ROM

1K x 16

BIOS and

Debug

Embedded

RAM

16K x 24

I/Os

Timers,

UARTs,

DataFlash,

Ports

ROUTER

Final ACC

MIX

Audio OUT

Audio IN

DSP Array (3 P24 DSPs)

Sync Bus

Async Bus

Audio I/O

External I/O