VGA7S019

Preliminary

TVS DIODE

UNISONICTECHNOLOGIESCO.,LTD

3 of 7

www.unisonic.com.tw

QW-R223-024.c

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PIN CONFIGURATION

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PIN DESCRIPTION

PIN NO.

PIN NAME

DESCRIPTION

1

VCC_SYNC

Isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated

ESD protection circuits

2

VCC_VIDEO

Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits

3

VIDEO1

4

VIDEO2

5

VIDEO3

High-speed ESD clamp input

6

GND

Ground

7

VCC_DDC

Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates

8

BYP

Bypass pin. Using a 0.2µF bypass capacitor will increase the ESD robustness of the

system.

9

DDC_OUT1

DDC signal output. Connects to the video connector side of one of the sync lines.

10

DDC_IN1

11

DDC_IN2

DDC signal input. Connects to the VGA controller side of one of the sync lines.

12

DDC_OUT2

DDC signal output. Connects to the video connector side of one of the sync lines.

13

SYNC_IN1

Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.

14

SYNC_OUT1

Sync signal buffer output. Connects to the video connector side of one of the sync lines

15

SYNC_IN2

Sync signal buffer input. Connects to the VGA controller side of one of the sync lines.

16

SYNC_OUT2

Sync signal buffer output. Connects to the video connector side of one of the sync lines