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TUSB8044AI 数据表(PDF) 48 Page - Texas Instruments |
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TUSB8044AI 数据表(HTML) 48 Page - Texas Instruments |
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48 / 63 page  GND GND UFP_VBUS UFP_VBUS 1uF C1 DP0M DP0P 8044_URX1M 8044_URX1P UFP_CC1 UFP_SBU1 UFP_SBU2 8044_UTX1M 8044_UTX1P DP1M DP1P 8044_DM 8044_DP 8044_DP 8044_DM 8044_UTX1M 8044_URX1P 8044_URX1M UFP_VBUS 90.9K 1% R1 10k 1% R2 GND UFP_CC1 DP1P DP0M DP0P DP1M VCONN 0.1uF C2 0.1uF C3 8044_UTX1P USB_SSTXP_UP 55 USB_SSTXM_UP 56 USB_SSRXP_UP 58 USB_SSRXM_UP 59 USB_DP_UP 53 USB_DM_UP 54 USB_VBUS 48 U1A TUSB8044ARGCR GND A1 SSTXp1 A2 SSTXn1 A3 VBUS A4 CC1 A5 Dp1 A6 Dn1 A7 SBU1 A8 VBUS A9 SSRXn2 A10 SSRXp2 A11 GND B12 SSRXp1 B11 SSRXn1 B10 VBUS B9 SBU2 B8 CC2 B5 VBUS B4 SSTXn2 B3 SSTXp2 B2 SHIELD S1 SHIELD S2 SHIELD S3 SHIELD S4 GND B1 GND A12 Type-C Plug 48 TUSB8044A SLLSF92 – FEBRUARY 2019 www.ti.com Product Folder Links: TUSB8044A Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Application (continued) 9.2.1.1 Design Requirements Table 43. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VDD Supply 1.1 V VDD33 Supply 3.3 V Upstream Port USB Support (SS, HS, FS) SS, HS, FS Downstream Port 1 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 2 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 3 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 4 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Number of Removable external exposed Downstream Ports 4 Number of Non-Removable external exposed Downstream Ports 0 Full Power Management of Downstream Ports Yes. (FULLPWRMGMTZ = 0) Individual Control of Downstream Port Power Switch Yes. (GANGED = 0) Power Switch Enable Polarity Active High. (PWRCTL_POL = 1) Battery Charge Support for Downstream Port 1 Yes Battery Charge Support for Downstream Port 2 Yes Battery Charge Support for Downstream Port 3 Yes Battery Charge Support for Downstream Port 4 Yes I2C EEPROM Support Yes 24MHz Clock Source Crystal 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Upstream Port Implementation The upstream of the TUSB8044A is connected to a USB Type-C captive cable. The system VBUS signal from the USB3 Type C plug is fed through a voltage divider. The purpose of the voltage divider is to make sure the system VBUS level meets TUSB8044A USB_VBUS input requirements. The voltage divider in this particular implementation will support up to 11.4V VBUS. If VBUS needs to be greater, then PD controller will need to directly control TUSB8044A USB_VBUS input. The USB-C plug has two pairs of USB 3.2 differential pairs (RX1/TX1 and RX2/TX2). In this particular example, one pair of super speed signals (RX2 and TX2) from Type-C plug is connected to the DP Hub/Retimer/Redriver. The other pair of super speed signals (RX1 and TX2) is routed to the TUSB8044A. The CC1 and VCONN signals from the Type-C plug is connected to the USB PD controller. Figure 37. Upstream Port Implementation |
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