PIC18LF4520ESLASHPSTQP datasheet(72/390 Pages) MICROCHIP

72 / 390 page

PIC18F2420/2520/4420/4520

DS39631A-page 70

Preliminary

 2004 Microchip Technology Inc.

The PLUSW register can be used to implement a form

of indexed addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

5.4.3.3

Operations by FSRs on FSRs

Indirect addressing operations that target other FSRs

or virtual registers represent special cases. For exam-

ple, using an FSR to point to one of the virtual registers

will not result in successful operations. As a specific

case, assume that FSR0H:FSR0L contains FE7h, the

address of INDF1. Attempts to read the value of the

INDF1 using INDF0 as an operand will return 00h.

Attempts to write to INDF1 using INDF0 as the operand

will result in a NOP.

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair but without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses indirect addressing.

Similarly, operations by indirect addressing are gener-

ally permitted on all other SFRs. Users should exercise

the appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

5.5

Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifi-

cally, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the intro-

duction of a new addressing mode for the data memory

space.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remain unchanged.

5.5.1

INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of indirect addressing using the FSR2

conditions, instructions that use the Access Bank – that

is, most bit-oriented and byte-oriented instructions –

can invoke a form of indexed addressing using an

offset specified in the instruction. This special address-

ing mode is known as Indexed Addressing with Literal

Offset, or Indexed Literal Offset mode.

When

using

the

extended

instruction

set,

this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the instruc-

tion is not interpreted as the lower byte of an address

(used with the BSR in direct addressing), or as an 8-bit

address in the Access Bank. Instead, the value is

interpreted as an offset value to an address pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

5.5.2

INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct

addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instructions that only use Inherent or Literal Addressing

modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or include a file address of 60h

or above. Instructions meeting these criteria will

continue to execute as before. A comparison of the dif-

ferent possible addressing modes when the extended

instruction set is enabled in shown in Figure 5-9.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 24.2.1

“Extended Instruction Syntax”.

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