2

RT8105

www.richtek.com

DS8105-03 April 2011

Functional Pin Description

BOOT (Pin 1)

Bootstrap supply pin for the upper gate driver. Connect

the bootstrap capacitor between BOOT pin and the PHASE

pin. The bootstrap capacitor provides the charge to turn

on the upper MOSFET.

UGATE (Pin 2)

Upper gate driver output. Connect to the gate of high side

power N-MOSFET. This pin is monitored by the adaptive

shoot-through protection circuitry to determine when the

upper MOSFET has turned off.

GND (Pin 3)

Both signal and power ground for the IC. All voltage levels

are measured with respect to this pin. Ties the pin directly

to the low side MOSFET source and ground plane with

the lowest impedance.

LGATE (Pin 4)

Lower gate drive output. Connect to the gate of low side

power N-MOSFET. This pin is monitored by the adaptive

shoot-through protection circuitry to determine when the

lower MOSFET has turned off.

VCC (Pin 5)

Connect this pin to a well-decoupled 5V or 12V bias

supply. It is also the positive supply for the lower gate

driver, LGATE.

FB (Pin 6)

Switcher feedback voltage. This pin is the inverting input

of the error amplifier. FB senses the switcher output

through an external resistor divider network.

OPS (OCSET, POR and Shut-Down) (Pin 7)

This pin provides multi-function of the over-current setting,

UGATE turn-on POR sensing, and shut-down features.

pins sets the over-current trip point.

Pulling the pin to ground resets the device and all external

MOSFETs are turned off allowing the output voltage power

rails to float.

issues an internal POR signal.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET and

the drain of the lower MOSFET.

Typical Application Circuit

2%)

(0.8V

voltage

reference

Internal

:

V

)

R2

R3

(1

V

V

REF

REF

OUT

±

+

×

=

BOOT

VCC

PHASE

UGATE

OPS

LGATE

FB

GND

1

5

6

3

2

8

7

4

10

1µF

3µH

+5V to +12V

0.1µF

470µF

1000µFx3

32

68

3904

MU

ML

0.1 to 0.33µF

1µF

200 to 1k

RT8105

+3.3V/+5V/+12V

BAT54

R1

C1

C2

R2

R3

R4

C3

C4

C5

C6 to C8

D1

L1

Q1

Q2

Q3

Disable >

0

0

R

C