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STC89LE53RC 数据表(PDF) 5 Page - STCmicro Technology Co,.Ltd |
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STC89LE53RC 数据表(HTML) 5 Page - STCmicro Technology Co,.Ltd |
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5 / 165 page ![]() 1.2 Block diagram The CPU kernel of STC89xx series are fully compatible to the standard 8051 microcontroller, maintains all instruction mnemonics and binary compatibility. STC89xx series can execute the fastest instructions per 6 clock cycles or 12 clock cycles(as the same as the standard 80C51) . Improvement of individual programs depends on the actual instructions used. STC89xx Block Diagram 256 Byte RAM RAM ADDR Register FLASH 64K Program Counter B Register ACC TMP2 TMP1 Stack Poniter ALU PSW Port 0,1,2,3,4 Latch WDT Control Unit XTAL2 XTAL1 RESET AUX-RAM 1024 Byte ISP/IAP Address Generator Timer 0/1 UART Port 0,1,2,3,4 Driver P0, P1,P2,P3,P4 PSEN Timer 2 ALE EA 5 |
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