AXP288D datasheet(39/110 Pages) XPOWER

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AXP288

PMIC Optimized For Multi-Core High-Performance System

AXP288 Datasheet V1.06

CHT SoC initiated global reset sequence

PLTRST_B

SLP_S0IX_B

COREPWROK

VCCAPWROK

VGG

VCC

Signals from SoC

VBOOT

Non-default on

rails

Power up triggered based on

SLP_S0IX_B signal rising edge

Figure 9-14

Note:

•

Power down and power up timing follow cold off and cold boot timing

•

Rail power up sequencing will wait until SLP_S0IX_B signal goes high to begin the sequence

•

If SLP_S0IX_B signal goes high before power down sequence completes, power down sequence should complete before power up begins

•

PLTRST_B to SLP_S0IX_B delay could be zero

Table 9-13

Parameter

Description

Min

Typical

Max

Units

Time that the SLP_S0IX_B signal stays

low

No max

Time for which rails stay down before

power up sequence begins

9.1.5 Sleep state control

Description:

1. Set the REG 9AH - REG 9EH

2. SOC set SLP_S0IX_B low, the power rails power down

3. SOC set SLP_S0IX_B high, the power rails power up

Default rail status

The following table is a list of the default on rails. The table also shows what the rail status is during sleep.

AXP288D 数据表(PDF) 39 Page - Shenzhen X-Powers Technology Co ., Ltd

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