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RFbeam Microwave GmbH | Schuppisstrasse 7 | CH-9016 St. Gallen | www.rfbeam.ch | K-MD2 Engineering Sample | data sheet

07/2018 – Revision A | Page 20/23

Commands

The commands are sent to the radar to set configurations. The payload length may be zero or four bytes. This

chapter provides detailed information about the commands of the K-MD2.

Header

Description

Datatype

Length

INIT

Run the initialization sequence and load the configuration files

-

0

RSID

Radar initial delay [clk]. The delay before the ramp starts in every chirp. The core clock is 38461538Hz.

0-32768

See chapter “Speed and Range Settings” for more information

UINT16

4

RSSF

Radar start frequency [MHz]

23800–24800

See chapter “Speed and Range Settings” for more information

UINT16

4

RSBW

Radar bandwidth [MHz]

100–1000

See chapter “Speed and Range Settings” for more information

UINT16

4

RSRG

Radar receiver gain [dB]

0–80

UINT8

4

PSMC

Receivers to include in mean range-doppler map

0x01 = RX1 0x02 = RX2 0x04 = RX3

Can be “OR” bit coded

UINT8

4

PSPT

Processor peak detection threshold

0–32768

See chapter “Peak Threshold” for more information

UINT16

4

PSRC

Processor range compensation for threshold

0.0–5.0

See chapter “Range Compensation” for more information

FLOAT

4

PSNP

Processor maximum number of peaks

0–200

UINT8

4

PSBU

Processor background update rate

0, 2, 4, 8, 16, 32, 64, 128, 256

See chapter “Background Update” for more information

UINT16

4

PSBR

Processor peak detection minimum range [bin]

2–254

UINT8

4

PSTR

Processor peak detection maximum range [bin]

2–254

UINT8

4

PSBS

Processor peak detection minimum speed [bin]

0–126

UINT8

4

PSTS

Processor peak detection maximum speed [bin]

0–126

UINT8

4

PSSM

Processor smooth mean range-doppler map

0x00 = Off 0x01 = On

See chapter “Smoothing” for more information

UINT8

4

PSNT

Processor maximum number of tracks to report

0–200

UINT8

4

PSRJ

Processor maximum range jitter [bin]

0–10

See chapter “Range and Speed Jitter” for more information

UINT8

4

PSSJ

Processor maximum speed jitter [bin]

0–10

See chapter “Range and Speed Jitter” for more information

UINT8

4

PSBL

Processor minimum track life [frame]

0–255

See chapter “Track Life” for more information

UINT8

4

PSTL

Processor maximum track life [frame]

0–255

See chapter “Track Life” for more information

UINT8

4