ALC658

Datasheet

Six-Channel AC’97 2.3 Audio Codec

Rev. 1.3

41

9.

Design and Layout Guide

9.1. Clocking

The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different

configurations is listed below:

Table 64. Clocking

Configuration

Operation & ID0

Pin-46 (XTLSEL)*

ID0

BIT-CLK

Clock Source

NC

0 (Primary)

Output 12.288MHz

Crystal or ext. 24.576MHz is attached at XTL-IN

Low**

0 (Primary)

Output 12.288MHz

Crystal or ext. 14.318MHz is attached at XTL-IN

NC

0 (Primary)

Input

12.288M input at BIT-CLK***

*Pin-46 is internally pulled high by a weak resistor.

**Low: Pulled low by a 0 ohm resistor. NC: Not Connected or pulled high.

***According to AC’97 ver 2.3, in Primary Mode, if a clock is present at BIT-CLK pin for at least 5 cycles before RESET# is

de-asserted, the ALC658 is a consumer of BITCLK. The ALC658 uses external 12.288MHz BITCLK as its clock source.

9.2. AC-Link

When the ALC658 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK.

When the ALC658 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK.

The ALC658 will return any uninstalled bits or registers with 0 for read operations. The ALC658 also stuffs the

unimplemented slot or bit with 0’s in SDATA_IN. Note that AC-LINK is MSB-justified.

Refer to “Audio CODEC ’97 Component Specification Revision 2.3.” for details.

Table 65. AC-Link

Slot#

0

1

2

3

4

5

6

7

8

9

10

11

12

SDATA-

OUT

TAG

CMD

DATA

PCM

L

PCM

R

CEN

SURR

L

SURR

R

LFE

S/PDIF

L

S/PDIF

L

SDATA-IN

TAG

ADD

DATA

PCM

L

PCM

R

Default ALC658 Slot Arrangement – CODEC ID = 00 (the ALC658 supports primary mode only)

SYNC