HT2273

8/10

Current Mode PWM Controller

www.hotchip.com.cn

Ver1.0

Oscillator Operation

The switching frequency is internally fixed at

65kHz.No external frequency setting components

are required for PCB design simplification.

Current Sensing and Leading Edge

Blanking

Cycle-by-Cycle current limiting is offered in HT2273.

The switch current is detected by a sense resistor

into the sense pin. An internal leading edge

blanking circuit chops off the sense voltage spike at

initial MOSFET on state due to snubber diode

reverse recovery so that the external RC filtering on

sense input is no longer required. The current limit

comparator is disabled and thus cannot turn off the

internal MOSFET during the blanking period. PWM

duty cycle is determined by the current sense input

voltage and the FB input voltage.

Internal Synchronized Slope

Compensation

Built-in slope compensation circuit adds slope

voltage onto the current sense input voltage for

PWM generation. This greatly enhances the close

loop stability at CCM and prevents possible

subharmonic oscillation and thus reduces the

output ripple voltage.

Gate Drive

The gate drive strength which is too weak leads to

over switch loss of MOSFET while too strong gate

drive output compromises in the over EMI. A good

tradeoff between output strength and dead time

control is achieved through the design of the built-in

totem pole gate. The low standby dissipation and

good EMI system design is easier to achieve

through this dedicated devise. For MOSFET gate

protection, an internal 12V clamp is added at higher

than expected VCC input.

Protection Controls

Excellent system stability is achieved by the

comprehensive protection of HT2273. Including

Cycle-by-Cycle current limiting (OCP), Over Load

Protection (OLP) and over voltage clamp, VCC

Clamp, Under Voltage Lockout on VCC (UVLO),

OTP and OVP shut down latch. At overload

condition when FB input voltage exceeds power

limit threshold value for more than TD_PL, control

circuit reacts to shut down the output power

MOSFET. Device restarts when VCC voltage drops

below UVLO limit. It is clamped when VCC is

higher than threshold value. The power MOSFET is

shut down when VCC drops below UVLO limit and

device enters power on start-up sequence

thereafter.