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Z86C34 数据表(PDF) 21 Page - Zilog, Inc.

部件名 Z86C34
功能描述  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z86C34 数据表(HTML) 21 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8® MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
21
Table 9. Handshake Timing1
TA = 0°C to +70°C
TA = –40°C to +105°C
12 MHz
16 MHz
12 MHz
16 MHz
Data
Direction
No
Symbol
Parameter
VCC
2
Min Max Min Max Min Max Min Max
1
TsDI(DAV)
Data In Setup Time
3.0V
0
0
0
0
IN
5.5V
0
0
0
0
IN
2
ThDI(RDY)
Data In Hold Time
3.0V
0
0
0
0
IN
5.5V
0
0
0
0
IN
3
TwDAV
Data Available Width
3.0V
155
155
155
155
IN
5.5V
110
110
110
110
IN
4
TdDAVI(RDY)
DAV Fall to RDY Fall
Delay
3.0V
0
0
0
0
IN
5.5V
0000
IN
5
TdDAVId(RDY) DAV Out to DAV Fall
Delay
3.0V
120
120
120
120
IN
5.5V
80
80
80
80
IN
6
RDY0d(DAV)
RDY Rise to DAV Fall
Delay
3.0V
0000
IN
5.5V
0000
IN
7
TdD0(DAV)
Data Out to DAV Fall
Delay
3.0V
42
31
42
31
OUT
5.5V
42
31
42
31
OUT
8
TdDAV0(RDY)
DAV Fall to RDY Fall
Delay
3.0V
0000
OUT
5.5V
0000
OUT
9
TdRDY0(DAV)
RDY Fall to DAV Rise
Delay
3.0V
160
160
160
160
OUT
5.5V
115
115
115
115
OUT
10
TwRDY
RDY Width
3.0V
110
110
110
110
OUT
5.5V
80
80
80
80
OUT
11
TdRDY0d(DAV) RDY Rise to DAV Fall
Delay
3.0V
110
110
110
110
OUT
5.5V
80
80
80
80
OUT
Note:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V.



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