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BK2425 数据表(PDF) 13 Page - List of Unclassifed Manufacturers

部件名 BK2425
功能描述  Low Power High Performance 2.4 GHz GFSK Transceiver
PDF  30 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

BK2425 数据表(HTML) 13 Page - List of Unclassifed Manufacturers

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BK2425
Revision 1.0
Proprietary and Confidential
Page 13 of 30
ACTIVATE
0101 0000
1
This write command followed by data 0x73 activates
the following features:
• R_RX_PL_WID
• W_ACK_PAYLOAD
• W_TX_PAYLOAD_NOACK
A new ACTIVATE command with the same data
deactivates them again. This is executable in power
down or stand by modes only.
The R_RX_PL_WID, W_ACK_PAYLOAD, and
W_TX_PAYLOAD_NOACK features registers are
initially in a deactivated state; a write has no effect, a
read only results in zeros on MISO. To activate these
registers, use the ACTIVATE command followed by
data 0x73. Then they can be accessed as any other
register. Use the same command and data to
deactivate the registers again.
This write command followed by data 0x53 toggles
the register bank, and the current register bank
number can be read out from REG7 [7]
R_RX_PL_WID
0110 0000
Read RX-payload width for the top
R_RX_PAYLOAD in the RX FIFO.
W_ACK_PAYLOAD
1010 1PPP
1 to 32
LSB byte first
Used in RX mode.
Write Payload to be transmitted together with
ACK packet on PIPE PPP. (PPP valid in the range
from 000 to 101). Maximum three ACK packet
payloads can be pending. Payloads with same PPP are
handled using first in - first out principle. Write
payload: 1– 32 bytes. A write operation always starts
at byte 0.
W_TX_PAYLOAD_NO
ACK
1011 0000
1 to 32
LSB byte first
Used in TX mode. Disables AUTOACK on this
specific packet.
NOP
1111 1111
0
No Operation. Might be used to read the STATUS
register
Table 2 SPI command
6.3.2
SPI Timing
x
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
x
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
x
S 7
S 6
S 5
S 4
S 3
S 2
S 1
S 0
H i - Z
0
0
0
0
0
0
0
0
H I - Z
x
x
S 7
S 6
S 5
S 4
S 3
S 2
S 1
S 0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S C K
C S N
M O S I
M I S O
M I S O
M O S I
W r i t e t o S P I r e g i s t e r:
R e a d f r o m S P I r e g i s t e r:
C 7
C 6
C 5
C 4
C 3
C 2
C 1
C 0
x
x
Figure 6 SPI timing



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