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BQ27Z561-R1 数据表(PDF) 18 Page - Texas Instruments |
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BQ27Z561-R1 数据表(HTML) 18 Page - Texas Instruments |
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18 / 24 page ![]() SDA/ HDQ SCL NU PULS VSS BAT_ SNS CE BAT INT TS SRN SRP PACK - BAT - RSENSE Battery BAT_SNS at Battery terminal No contact to NU (BAT_SNS trace on bottom layer) RSRN RSRP BAT + PACK + Weld Tab Weld Tab Tab + Tab - 18 BQ27Z561-R1 SLUSDH5 – MARCH 2019 www.ti.com Product Folder Links: BQ27Z561-R1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Layout Guidelines (continued) • The BQ27Z561-R1 has an internal LDO that is internally compensated and does not require an external decoupling capacitor. • The I2C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener diode and series resistor provides more robust ESD performance. The I2C clock and data lines have an internal pull-down. When the gas gauge senses that both lines are low (such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP mode to conserve power. 11.2 Layout Example Figure 10. BQ27Z561-R1 Key Trace Board Layout |
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