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FS970X 数据表(PDF) 21 Page - Fortune Semiconductor Corp. |
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FS970X 数据表(HTML) 21 Page - Fortune Semiconductor Corp. |
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21 / 46 page  FS970X Rev. 4.4 21/46 CPL is the negative input of CMP1, controlled by cap, cntd, SCMPL1:0, CAPM, and CAPTG. Details are shown in Chart 14. When cap=0 and cntd=0, the output of CPL is irrelevant to CAPM and CAPTG. It is directly selected by SCMPL1:0. When cap=0 and cntd=1, it’s under short testing mode. The output of CPL is fixed to be Vcntd. When cap=1, it’s under capacitor measuring mode. At this time, the output of CPL is irrelevant to cntd and SCMPL1:0. When CAPM=0, it means low and medium capacity measuring. The output of CPL is controlled by CAPTG; they are Vcapc1 and Vcapd1. When CAPM=1, it means high capacity measuring. The output of CPL is controlled by CAPTG. They are Vcapc2 and Vcapd2. I N P U T cap 0 0 0 0 0 1 1 1 1 cntd 0 0 0 0 1 x x X x SCMPL1:0 00 01 10 11 xx xx xx Xx xx CAPM x x X x x 0 0 1 1 CAPTG x x X x x 0 1 0 1 OUTPUT CPL AGND Vsrc1 Vcapc2 Vrfh Vcntd Vcapc1 Vcapd1 Vcapc2 Vcapd2 Chart 14 CPL multiplexers setup. |
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