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FS9721_LP3 数据表(PDF) 9 Page - Fortune Semiconductor Corp. |
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FS9721_LP3 数据表(HTML) 9 Page - Fortune Semiconductor Corp. |
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9 / 39 page ![]() FS9721_LP3 Rev. 2.1 9/39 8. Dice Pad Layout & Pad Coordinate 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 78 36, first bonding Substrate should be connected to VSS. Pad opening: 90µm. Chip size: 3.24mm×2.58mm. Diagram 3 78PIN Dice PadNo Name X[mm] Y[mm] PadNo. Name X[mm] Y[mm] 1 OP2N 0.264 0.077 40 CB 2.974 2.495 2 OP2O 0.404 0.077 41 CA 2.834 2.495 3 ADIP 0.544 0.077 42 VGG 2.694 2.495 4 ADIN 0.669 0.077 43 VDDA 2.569 2.495 5 SA 0.794 0.077 44 RLCD 2.444 2.495 6 SGND 0.919 0.077 45 XIN 2.319 2.495 7 ADP 1.044 0.077 46 XOUT 2.194 2.495 8 DT 1.169 0.077 47 TXD 2.069 2.495 9 SMV 1.294 0.077 48 SEG14 1.923 2.495 10 CRES1 1.419 0.077 49 SEG13 1.798 2.495 11 RL 1.544 0.077 50 SEG12 1.673 2.495 12 N.C 1.669 0.077 51 SEG11 1.548 2.495 |
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