FS9952_LP1

Rev. 2.0

25/31

15.10

AC Rectification Circuit

Diagram 22 is the average rectification circuitry of FS9952_LP1. In the circuit, AC signals enter IC through

R23, and then in the process of voltage division through R23, R22, R21, R20 and R19. The divided AC signals

come out from OP1O pin and enter IC through ADIP pin and ADIN pin after rectification. VR1 can adjust the

signal size to be the calibration of AC measurement.

200mV mode is amplified 10 times through OP.

Diagram 23 is the peak value rectification circuitry. Diagram 24 is the true valid value rectification circuitry.

The user can determine by oneself according to the need to select which rectification circuit to use.

+

_

+

-

+

-

R5

10k

R8

90k

R12

28.5k

R13

22k

R11

22k

D1

D2

R24

100k

R25

100k

To DIGIT Part

To ADC V+

To ADC V+

To ADC V-

INL

INH

AD1P

AD1N

OP2O

OP2N

OP2P

OP1O

OP1N

VR1

2k

C13

27nF

C12

27nF

C9

0.47uF

C10

0.47uF

C6

4.7uF

2

3

1

64

62

63

61

FS9952

Diagram 22

Average Rectification Circuit

+

_

+

_

+

_

R8

90k

R5

10k

C6

4.7uF

R12

VR1

R11

22k

R13

22k

D1

D2

C12

27nF

To Digit Part

INL

INH

To ADC V-

To ADC V+

AD1P

AD1N OP2O

OP2N

OP1O

OP1N

To ADC V+

FS9952

OP2P

Diagram 23

Peak Value Rectification Circuit

Full

Wave

Rectifier

Bias

Section

RMS

core

+

_

Input Ampcifier

1

2

3

4

5

6

7

8

FS9952

33uF

1uF

10uF

1uF

0.1uF

38 VGG

62 OP1O

2 AD1P

3 AD1N

VSS

AD737

28k

1k

8k

8k

100k

Diagram 24

True Valid Value Rectification Circuit