Rev. G 08/16

7

TOP221-227

www.power.com

20 W Universal Supply using 8 Lead PDIP

Figure 8 shows a 12 V, 20 W secondary regulated flyback

power supply using the TOP224P in an eight lead PDIP

package and operating from universal 85 to 265 VAC input

voltage. This example demonstrates the advantage of the

higher power 8 pin leadframe used with the TOPSwitch-II

family. This low cost package transfers heat directly to the

board through six source pins, eliminating the heatsink and

the associated cost. Efficiency is typically 80% at low line

input. Output voltage is directly sensed by optocoupler U2

and Zener diode VR2. The output voltage is determined by

the Zener diode (VR2) voltage and the voltage drops across

the optocoupler (U2) LED and resistor R1. Other output

voltages are possible by adjusting the transformer turns ratio

and value of Zener diode VR2.

AC power is rectified and filtered by BR1 and C1 to create

the high voltage DC bus applied to the primary winding of

T1. The other side of the transformer primary is driven by

the integrated TOPSwitch-II high-voltage MOSFET. D1 and

VR1 clamp leading-edge voltage spikes caused by trans-

former leakage inductance. The power secondary winding

is rectified and filtered by D2, C2, L1, and C3 to create the

12 V output voltage. R2 and VR2 provide a slight pre-load

on the 12 V output to improve load regulation at light loads.

The bias winding is rectified and filtered by D3 and C4 to

create a TOPSwitch bias voltage. L2 and Y1-safety capaci-

tor C7 attenuate common mode emission currents caused

by high-voltage switching waveforms on the DRAIN side of

the primary winding and the primary to secondary capaci-

tance. Leakage inductance of L2 with C1 and C6 attenu-

ates differential-mode emission currents caused by the

fundamental and harmonics of the trapezoidal or triangular

primary current waveform. C5 filters internal MOSFET gate

drive charge current spikes on the CONTROL pin, deter-

mines the auto-restart frequency, and together with R1 and

R3, compensates the control loop.

Figure 8. Schematic Diagram of a 20 W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.

PI-2019-033197

D2

MUR420

D3

1N4148

C2

330

µF

35 V

C3

220

µF

35 V

T1

D1

BYV26C

VR1

P6KE200

VR2

1N5241B

11 V

R2

220

Ω

BR1

400 V

C1

47

µF

400 V

F1

3.15 A

J1

C6

0.1

µF

250 VAC

L2

22 mH

L

N

C5

47

µF

U1

TOP224P

D

S

C

CONTROL

TOPSwitch-II

R3

6.8

Ω

L1

3.3

µH

C4

0.1

µF

U2

PC817A

R1

100

Ω

C7

1 nF

250 VAC

Y1

+12 V

RTN