Low-cost 3.3V Zero Delay Buffer
CY2305
CY2309
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07140 Rev. *C
Revised December 14, 2002
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low-skew outputs
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY2305)
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY2309)
• Less than 200 ps cycle-cycle jitter, compatible with
Pentium-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309
only [see “Select Input Decoding” on page 2])
• Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil
SOIC package (CY2305)
• 3.3V operation
• Industrial temperature available
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0
µA of current draw for commercial temper-
ature devices and 25.0
µA for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input
to output propagation delay on both devices is guaranteed to
be less than 350 ps, and the output to output skew is
guaranteed to be less than 250 ps.
The CY2305/CY2309 is available in two/three different config-
urations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
SOIC/TSSOP
Top View
Pin Configuration
2309-1
2309-2
1
2
3
4
5
8
7
6
REF
CLK2
CLK1
GND
VDD
CLKOUT
CLK4
CLK3
SOIC
Top View
2309-3
PLL
MUX
Select Input
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
CLKOUT
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