N3291xUxDN Data Sheet

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Nuvoton Technology Corp.

Release Date: Jun. 2013

http://www.nuvoton.com/

Revision A3



UART



A high speed UART supported:



Baud rate is up to 1M bps.



4 signals TX, RX, CTS and RTS supported.



A normal UART supported:



Baud rate is up to 115.2K bps.



2 signals TX and RX supported only.



SPI



Two SPI interfaces are supported.



Both master and slave mode are supported in SPI interface 0.



Only master mode is supported in SPI interface 1.



Byte transfer with configurable stop interval supported.



I2C



One I2C channel supported.





Multi-master operation supported.



Advanced Interrupt Controller



Total 32 interrupt source supported.



Configurable interrupt type:



Low-active level triggered interrupt.



High-active level triggered interrupt.



Low-active edge (falling edge) triggered interrupt.



High-active edge (rising edge) triggered interrupt.



Individual interrupt mask bit for each interrupt source.



8 different priority levels supported.



Daisy-chain priority mechanism supported for interrupts with same priority level.



Low priority interrupt automatic masking supported for interrupt nesting.



RTC



Independent power plane supported



Dual clock source are supported, accurate 32.768 KHz crystal oscillation circuit and built-

in coarse 32KHz RC-oscillator.



Time counter (second, minute, hour) and Calendar counter (day, month, year) supported.



Alarm supported (second, minute, hour, day, month and year).



12/24-hour mode and Leap year supported.



Alarm to wake chip up from Standby mode or from Power-down mode supported.



Wake chip up from Power-down mode by input pin supported.



Power-off chip by register setting supported.



Power-on timeout is supported for low battery protection.



GPIO



88 programmable general purpose I/Os supported and separated into 5 groups.



Individual configuration supported for each I/O signal.



Configurable interrupt control functions supported.



Configurable de-bounce circuit supported for interrupt function.