6/17

¡ Semiconductor

MSM7580

SYNCA1 , SYNCA2

Synchronous signal input pins.

SYNCA1 and SYNCA 2 control the ADPCM data input/output timing for Channel 1 (SIA1,

SOA1) and Channel 2 (SIA2, SOA2), respectivery.

The ADPCM data can be input or output with timing other than the PCM data interface.

Therefore PCM and ADPCM interfaces can be used at a mutually independent timing except

some timing.

Since master clocks are generated by the internal PLL using SYNCA, a synchronous signal

should be input to there pins.

Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the

timing described in "Notes on Usage" should not be used.

DET1, DET2

Special ADPCM input data pattern detect pins.

When a 4-bit continuous "0" pattern at the ADPCM input pins Channel 1 (STA1) and Channel 2

(SIA2) is detected, DET1 and DET2 go from a digital "0" to a digital "1" state.

A digital "1" is output at the rising edge of the clock.

The fourth data bit (LSB) is clocked into the register by the bit clock (BCLKA) and the held there

until the rising edge in the next time frame.

When detecting the special data pattern in the next time frame, the digital "1" on the pins DET

(1, 2) is remains. When the THR1 pin or THR2 pin is at digital "1" level, the functions of these pins

are invalid.

RES1, RES2

Algorithm reset signal input pins for Channel 1 (RES1) and Channel 2 (RES2).

When a digital “0” is applied, the entire transcoder goes to its initial state.

This reset is defined by ITU-T G.721 and is an optional reset.

BCLKA

Bit clock input pin used to define the data transmission speed at the ADPCM interface.

This pin can be used for Channels 1 and 2, which allows the ADPCM data interface speed to be

defined differently than the PCM data interface speed.

Power supply.

The device must operate at +5 V

±10%.