G52220-0, Rev 4.1

© VITESSE SEMICONDUCTOR CORPORATION

Page 9

1/8/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8116

ATM/SONET/SDH 622/155Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Table 5: Receive High Speed Data Input Timing Table

(STS-3 Operation)

Figure 8: Transmit Data Input Timing Diagram

Table 6: Transmit Data Input Timing Table

(STS-12 Operation)

Table 7: Transmit Data Input Timing Table

(STS-3 Operation)

Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case

Parameter

Description

Min

Typ

Max

Units

Receive clock period

-

6.43

-

ns

Serial data setup time with respect to RXCLKIN

1.5

-

-

ns

Serial data hold time with respect to RXCLKIN

1.5

-

-

ns

Parameter

Description

Min

Typ

Max

Units

Transmit data setup time with respect to TXLSCKOUT

1.0

-

-

ns

Transmit data hold time with respect to TXLSCKOUT

1.0

-

-

ns

Parameter

Description

Min

Typ

Max

Units

Transmit data setup time with respect to TXLSCKOUT

1.0

-

-

ns

Transmit data hold time with respect to TXLSCKOUT

1.0

-

-

ns

TXLSCKOUT

TXIN [7:0]