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ALC662

Datasheet

5.1 Channel High Definition Audio Codec

Rev. 1.0

7.1.1.

Signal Definitions

Table 6.

Link RESET#

Item

Description

BCLK

24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.

SYNC

A 48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA

controller and connects to all codecs.

SDO

Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are

carried on SDO. The data rate is double-pumped; the controller drives data onto the SDO, the codec samples

data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one

SDO. To extend outbound bandwidth, multiple SDOs may be supported.

SDI

Serial Data Input signal driven by the codec. This is point-to-point serial data from the codec to the HDA

controller. The controller must support at least one SDI. Up to a maximum of 15 SDI’s can be supported.

SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of

BCLK. SDI can be driven by the controller to initialize the codec’s ID.

RESET#

Active low reset signal. Asserted to reset the codec to default power-on state. RESET# is sourced from the

HDA controller and connects to all codecs.

Table 7.

HDA Signal Definitions

Signal Name

Source

Type for Controller Description

BCLK

Controller

Output

Global 24.0MHz bit clock.

SYNC

Controller

Output

Global 48kHz Frame Sync and outbound tag signal.

SDO

Controller

Output

Serial data output from controller.

SDI

Codec/Controller

Input/Output

Serial data input from codec. Weakly pulled down by the

controller.

RESET#

Controller

Output

Global active low reset signal.

SDO

SYNC

SDI

BCLK

Start of Frame

8-Bit Frame SYNC

7654

999 998 997 996 995 994 993 992 991 990

499

498

497

496

495

494

Controller samples SDI at rising edge of BCLK

Codec samples SDO at both rising and falling edge of BCLK

Figure 4.

Bit Timing

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