DS1232LP/LPS

Low Power MicroMonitor Chip

www.artschip.com

1

FEATURES

Super-low power version of DS1232

50µA quiescent current

Halts and restarts an out-of-control microprocessor

Automatically restarts microprocessor after power failure

Monitors pushbutton for external override

Accurate 5% or 10% microprocessor power supply monitoring

8-pin DIP, 8-pin SOIC or space saving µ-SOP package

available

Optional 16-pin SOIC package available

Industrial temperature -40

℃ to +85℃ available, designated N

PIN DESCRIPTION

-Pushbutton Reset Input

TD

-Time Delay Set

TOL

-Selects 5% or 10% Vcc Detect

GND

-Ground

RST

-Reset Output (Active High)

-Reset Output (Active Low, open drain)

-Strobe Input

Vcc

-+5 Volt Power

PIN ASSIGNMENT

DS1232LP 8-Pin DIP (300-mil)

See Mech. Drawings Section

DS1232LPS 16-Pin SOIC (300-mil)

See Mech. Drawings Section

DS1232LPµ(118-mil µ-SOP)

See Mech. Drawings Section

DS1232LPS-2 8-Pin SOIC (150-mil)

See Mech. Drawings Section

DESCRIPTION

The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software

execution, and external over-ride. First, a precision temperature-compensated reference and comparator circuit monitors the status of

Vcc. When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces reset to the active state. When

Vcc returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 250ms to allow the power supply

and processor to stabilize.

The second function the DS1232LP/LPS performs is pushbutton reset control. The DS1232LP/LPS debounces the pushbutton input

and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232LP/LPS has an

internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer

function can be set to operate on timeout setting of approximately 150ms, 600ms, and 1.2 seconds.