DS9034PCX datasheet(4/11 Pages) ARTSCHIP

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DS1643/DS1643P

Nonvolatile Timekeeping RAM

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DS1643 REGISTER MAP-BANK1 Table 2

DATA

ADDRESS

FUNCTION

1FFF

YEAR

00-99

1FFE

MONTH

01-12

1FFD

DATE

01-31

1FFC

DAY

01-07

1FFB

HOUR

00-23

1FFA

MINUTES

00-59

1FF9

SECONDS

00-59

1FF8

CONTROL

= STOP BIT

R=READ BIT

FT=FREQUENCY TEST

W=WRITE BIT

X=UNUSED

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1643 is in the read mode whenever

(write enable) is high and

(chip enable) is low. The device architecture

allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA

after the last address input is stable, providing that the

and

access times and states are satisfied. If

access

times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The

state of the data input/output pins (DQ) is controlled by

and

. If the outputs are activated before tAA, the data lines are

driven to an intermediate state until tAA. If the address inputs are changed while

and

remain valid, output data will

remain valid for output data hold time (tOH) but will then go indeterminate until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1643 is in the write mode whenever

and

are in their active state. The start of a write is referenced to the latter

occurring transition of

. The addresses must be held valid throughout the cycle.

must return inactive for a

minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain

valid for tDH afterward. In a typical application, the

signal will be high during a write cycle. However,

can be active

provided that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low the data bus can

become active with read data defined by the address inputs. A low transition on

will then disable the outputs tWEZ after

goes active.

DATA RETENTION MODE

When Vcc is within nominal limits (Vcc >4.5 volts) the DS1643 can be accessed as described above with read or write cycles.

However, when Vcc is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM

are blocked from access. This is accomplished internally by inhibiting access via the

signal. At this time the power-on reset

output signal (

) will be driven active low and will remain active until Vcc returns to nominal levels. When Vcc falls below the

level of the internal battery supply, power input is switched from the Vcc pin to the internal battery and clock activity, RAM, and

clock data are maintained from the battery until Vcc is returned to nominal level. The

signal is an open drain output and

requires a pull up. Except for the

, all control, data and address signals must be powered down when Vcc is powered down.

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