AD9958SLASHPCB datasheet(7/40 Pages) AD

7 / 40 page

AD9958

Rev. 0 | Page 7 of 40

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

IAVDD

—Both Channels On, Sweep Accumulator,

REF_CLK Multiplier and 10-Bit Output Scalar Enabled

110

IDVDD

—Both Channels On, Single Tone Mode

IDVDD

—Both Channels On, Sweep Accumulator,

REF_CLK Multiplier and 10-Bit Output Scalar Enabled

IDVDD_I/O

IDVDD = read

IDVDD_I/O

IDVDD = write

IAVDD Power-Down Mode

2.5

IDVDD Power-Down Mode

2.5

DATA LATENCY (PIPELINE DELAY) SINGLE TONE MODE2, 3

Frequency, Phase, and Amplitude Words to DAC Output

w/Matched Latency Enabled

Sys Clk

Frequency Word to DAC Output w/Matched Latency

Disabled

Sys Clk

Phase Offset Word to DAC Output w/Matched Latency

Disabled

Sys Clk

Amplitude Word to DAC Output w/Matched Latency

Disabled

Sys Clk

DATA LATENCY (PIPELINE DELAY) MODULATION MODE3, 4

Frequency Word to DAC Output

Sys Clk

Phase Offset Word to DAC Output

Sys Clk

Amplitude Word to DAC Output

Sys Clk

DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE3, 4

Frequency Rising/Falling Delta Tuning Word to DAC

Output

Sys Clk

Phase Offset Rising/Falling Delta Tuning Word to DAC

Output

Sys Clk

Amplitude Rising/Falling Delta Tuning Word to DAC

Output

Sys Clk

1 For the VCO frequency range of 160 MHz to 255 MHz there is no guarantee of operation.

2 Data latency is reference to the I/O_UPDATE>

3 Data latency is fixed.

4 Data latency is referenced to a profile change.

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AD9958/PCB 数据表(PDF) 7 Page - Analog Devices

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