5403AS–BDC–10/04

Features

Ω or Single-ended 50Ω Analog Input

Ω Differential or Single-ended 50Ω Clock input

– ADC Gain Adjust

– Sampling Delay Adjust

– 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs

– Data Ready Output with Asynchronous Reset

– Out-of-range Output Bit (11th Bit)

– Cavity Down EBGA 317 (Enhanced Ball Grid Array)

– 25 × 35 mm Overall Dimensions

Performances

•

3 GHz Full-power Analog Input Bandwidth

•

±0.4 dB Gain Flatness from DC up to 1.5 GHz

•

Single-tone Performance at Fs = 1.5 Gsps, Full Nyquist Zone

–

ENOB = 8.0 Effective Bits, F

–

SNR = 52 dB, SFDR = -60 dBFS, F

•

Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (-7 dBFS each tone)

–

Fin1 = 745 MHz, Fin2 = 755 MHz: IMD3 = -60 dBFS

–

Fin1 = 1244 MHz, Fin2 = 1255 MHz: IMD3 = -60 dBFS

Screening

•

Temperature Range:

–T

–T

Applications

•

Direct RF Down Conversion

•

Ultra Wide Band Satellite Receivers

•

Radars and Countermeasures

•

High-speed Acquisition Systems

•

High Energy Physics

•

Automatic Test Equipment

Description

The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4

DMUX, designed for accurate digitization of broadband signals.

It features 8.0 Effective Number of Bits (ENOB) and -60 dBFS Spurious Free Dynamic

Range (SFDR) at 1.5 Gsps over the full first Nyquist zone.

10-bit

1.5 Gsps ADC

With

1:4 DMUX

AT84AS003

Summary

This is a summary document. A complete document is not

available at this time. For more information, please contact

your local Atmel sales office.