5

AT84CS001

5402AS–BDC–11/04

B0N, B1N, B2N, B3N, B4N,

B5N, B6N, B7N, B8N, B9N

A5, A4, A3, A2, B1, C1, D1, E1,

F1, G1

Inverted phase (-) digital outputs for port B

BOR/DRBN

J2

In-phase (+) additional bit output for port B or inverted phase

(-) output clock in staggered mode for port B

BORN/DRB

H1

Inverted phase (-) additional bit output for port B or in-phase (+)

output clock in staggered mode for port B

C0, C1, C2, C3, C4, C5, C6,

C7, C8, C9

M2, N2, P2, R2, T2, U2, V2,

W2, V3, V4

In-phase (+) digital outputs for port C

C0 is the LSB, C9 is the MSB

C0N, C1N, C2N, C3N, C4N,

C5N, C6N, C7N, C8N, C9N

L1, M1, N1, P1, R1, T1, U1, V1,

W3, W4

Inverted phase (-) digital outputs for port C

COR/DRCN

V5

In-phase (+) additional bit output for port C or inverted phase

(-) output clock in staggered mode for port C

CORN/DRC

W5

Inverted phase (-) additional bit output for port C or in-phase (+)

output clock in staggered mode for port C

D0, D1, D2, D3, D4, D5, D6,

D7, D8, D9

V6, V7, V8, V9, V10, V11, V12,

V13, V14, V15

In-phase (+) digital outputs for port D

D0 is the LSB, D9 is the MSB

D0N, D1N, D2N, D3N, D4N,

D5N, D6N, D7N, D8N, D9N

W6, W7, W8, W9, W10, W11,

W12, W13, W14, W15

Inverted phase (-) digital outputs for port D

DOR/DRDN

V16

In-phase (+) additional bit output for port D or inverted phase

(-) output clock in staggered mode for port D

DORN/DRD

W16

Inverted phase (-) additional bit output for port D or in-phase (+)

output clock in staggered mode for port D

DR

J1

In-phase (+) data ready signal output

DRN

K2

Inverted phase (-) data ready signal output

DAO

R18

In-phase (+) output signal for standalone delay cell

DAON

R19

Inverted phase (-) output signal for standalone delay cell

Additional Functions

ASYNCRST

B17

Asynchronous reset signal

CLKTYPE

V18

Input clock type selection signal

DRTYPE

K1

Output clock type selection signal

CLKDACTRL

V19

Clock delay cell control signal

DACTRL

W18

Standalone delay cell control signal

DAEN

W17

Standalone delay cell enable signal

RS

L2

Ratio selection signal

SLEEP

A18

Sleep mode enable

STAGG

A17

Staggered output mode selection signal

BIST

V17

Built-in self test enable

DIODE

C19

Diode for die junction temperature monitoring

Table 2. Pin Description (Continued)

Symbol

Pin Number

Function