 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
BQ27Z561YPHT-R1 数据表(PDF) 7 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
BQ27Z561YPHT-R1 数据表(HTML) 7 Page - Texas Instruments |
|
|
7 / 26 page  7 BQ27Z561-R1 www.ti.com SLUSDH5 – MARCH 2019 Product Folder Links: BQ27Z561-R1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Used for ADC 7.14 Voltage Reference2 (REF2) Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF2 Internal Reference Voltage(1) 1.2 1.21 1.22 V VREF2_DRIFT Internal Reference Voltage Drift TA = –40 °C to 85°C –20 20 PPM/°C 7.15 Flash Memory Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Data retention 10 100 Years Flash programming write cycles Data Flash 20000 Cycles Instruction Flash 1000 Cycles t(ROWPROG) Row programming time 40 µs t(MASSERASE) Mass-erase time TA = –40°C to 85°C 40 ms t(PAGEERASE) Page-erase time TA = –40°C to 85°C 40 ms IFLASHREAD Flash Read Current TA = –40°C to 85°C 1 mA IFLASHWRTIE Flash Write Current TA = –40°C to 85°C 5 mA IFLASHERASE Flash Erase Current TA = –40°C to 85°C 15 mA 7.16 I 2C I/O Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage SCL, SDA/HDQ, VREG18 = 1.8 V 1.26 V VIL Low-level input voltage low VREG18 = 1.8 V 0.54 V VOL Low-level output voltage IOL = 1 mA, VREG18 = 1.8 V 0.36 V CI Input capacitance 10 pF Ilkg Input leakage current 1 µA 7.17 I 2C Timing — 100 kHz PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fSCL Clock Operating Frequency SCL duty cycle = 50% 100 kHz tHD:STA START Condition Hold Time 4.0 µs tLOW Low period of the SCL Clock 4.7 µs tHIGH High period of the SCL Clock 4.0 µs tSU:STA Setup repeated START 4.7 µs tHD:DAT Data hold time (SDA input) 0 ns tSU:DAT Data setup time (SDA input) 250 ns tr Clock Rise Time 10% to 90% 1000 ns tf Clock Fall Time 90% to 10% 300 ns tSU:STO Setup time STOP Condition 4.0 µs tBUF Bus free time STOP to START 4.7 µs 7.18 I 2C Timing — 400 kHz PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fSCL Clock Operating Frequency SCL duty cycle = 50% 400 kHz tHD:STA START Condition Hold Time 0.6 µs |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
