MPC7455 datasheet(49/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

System Design Information

Figure 24. PLL Power Supply Filter Circuit

9.3 Decoupling Recommendations

Due to the MPC7455 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7455 can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other components in the

MPC7455 system, and the MPC7455 itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pin

of the MPC7455. It is also recommended that these decoupling capacitors receive their power from separate VDD,

OVDD/GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors

should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along

the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design:

A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling

Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of

capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the

VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors

should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should

also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk

capacitors: 100–330 µ F (AVX TPS tantalum or Sanyo OSCON).

9.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.

Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC

(no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the MPC7455.

If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and L3VSEL should be

connected to BVSEL.

9.5 Output Buffer DC Impedance

The MPC7455 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To

measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor

is varied until the pad voltage is OVDD/2 (see Figure 25).

The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When

data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN

then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and

VDD

AVDD

Ω

2.2 µF

GND

Low ESL Surface Mount Capacitors

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