74HC02 datasheet(4/5 Pages) SS

4 / 5 page

High Speed CMOS Logic – 74HC02

DC Electrical Characteristics Continued (Voltages Referenced to GND)

Rev 1.0

22/04/19

LIMITS

PARAMETER

Not production tested in die form, characterized by chip design and tested in package LAT.

Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

SYMBOL

VCC

CONDITIONS

≤ 85°C

UNITS

0°C to 25°C

2.0V

1.9

4.5V

4.4

VIN = VIH or VIL

│IOUT│≤ 20µA

6.0V

5.9

3.0V

VIN = VIH or VIL

│IOUT│≤ 2.4mA

2.48

2.34

4.5V

VIN = VIH or VIL

│IOUT│≤ 4.0mA

3.98

3.84

Minimum High-Level

Output Voltage

VOH

6.0V

VIN = VIH or VIL

│IOUT│≤ 5.2mA

5.48

5.34

2.0V

0.1

4.5V

0.1

VIN = VIL or VIL

│IOUT│≤ 20µA

6.0V

0.1

3.0V

VIN = VIL or VIL

│IOUT│≤ 2.4mA

0.26

0.33

4.5V

VIN = VIL or VIL

│IOUT│≤ 4.0mA

0.26

0.33

Maximum Low-Level

Output Voltage

VOL

6.0V

VIN = VIL or VIL

│IOUT│≤ 5.2mA

0.26

0.33

Maximum Input

Leakage Current

IIN

6.0V

VIN = VCC or GND

±0.1

±1.0

µA

Maximum Quiescent

VIN = VCC or GND

Supply Leakage

Current

ICC

6.0V

IOUT = 0µA

µA

AC Electrical Characteristics3

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

UNITS

0°C to 25°C

≤ 85°C

2.0V

3.0V

4.5V

Maximum Propagation

Delay, Input A or B to

CL = 50pF,

Output Y

(Figure 1,2)

tPLH, tPHL

tr = tf = 6ns

6.0V

2.0V

3.0V

4.5V

Maximum Output Rise

and Fall Time,

CL = 50pF,

Any Output

(Figure 1,2)

tTLH, tTHL

tr = tf = 6ns

6.0V

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