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FP6329ASOGTR 数据表(PDF) 13 Page - Fitipower Integrated Technology Inc. |
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FP6329ASOGTR 数据表(HTML) 13 Page - Fitipower Integrated Technology Inc. |
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13 / 16 page ![]() 13 FP6329/A/B-1.0-APR-2010 FP6329/A 85T fitipower integrated technology lnc. Application Information (Continued) Frequency (Hz) FLC FESR -40dB/dec -20dB/dec 0 Figure26. Bode plot of open loop gain Proper Type Ⅲ compensation of the system closes the control loop to allow for a desired bandwidth with stability. The ideal Bode plot for compensation system should be satisfied two conditions; one is a gain that decline with -20dB/decade slope and cross 0dB at the predictable bandwidth. Another one is phase margin greater than 45° below the 0dB crossing. ) 9 C 4 R 1 S )( 5 C 4 C 6 R 5 C 4 C S ( S ) 5 C 6 R 1 S )( ) 4 R 3 R ( 9 C 1 S ( 4 C 4 R 3 R 4 R 3 R GAINTYPEIII Compensation break frequency equation 5 C 4 C 5 C 4 C 6 R 2 1 F 1 P , 9 C 4 R 2 1 F 2 P 5 C 6 R 2 1 F 1 Z , ) 4 R 3 R ( 4 R 2 1 F 2 Z Figure27 shows the transfer function of closed loop system with Type Ⅲ compensation. The Type Ⅲ compensation network applies two zeroes to give a 180° boost to the phase. This boost is necessary to contract the effect of an under damped at the double pole. Frequency (Hz) FLC FESR 0 FC FZ1 FZ2 FP1 FP2 Figure27. Bode plot of converter closed loop gain The following guidelines will help calculate the poles and zeroes of the compensation network. 1. Select R1, 1kΩ to 10kΩ typically. 2. Choose a gain (R6/R3) that will shift the open loop gain to the desired bandwidth, Fc (1/10 to 1/4 of Fsw). R6 can be calculated by the equation: MAX 3 LC C IN OSC 6 D R F F V V R where DMAX=1, since FP6329/A supports 100% duty cycle. VOSC=1.5V, the FP6329/A uses a 1.5V ramp amplitude. LC IN 3 C MAX 3 LC C IN OSC 6 F V R F 5 . 1 D R F F V V R 3. Calculate C5 to place first zero, FZ1, before FLC. FZ1 is adjustable from 0.1 to 0.75 of FLC. Usually pick the 0.5 factor. LC LC F 6 R 1 F 5 . 0 6 R 2 1 5 C 4. Calculate C4 to place first pole, FP1, at FESR. 1 ESR F 5 C 6 R 2 5 C 4 C 5. Calculate R4 to place second zero, FZ2, at the output filter double pole, FLC. 1 F F 3 R 4 R LC SW 6. Calculate C9 to place second pole, FP2, lower than FLC. FP2 is adjustable from 0.3 to 1.0 of FSW. Usually set the FP2 at half the switching frequency. Set FP2 lower in frequency helps reduce the gain of the compensation network in high frequency and minimize duty cycle jitter. SW SW F 4 R 1 F 5 . 0 4 R 2 1 9 C COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP GAIN R6 R3 20 log VIN VOSC 20 log (DMAX • ) |
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