DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Preliminary
7
Version: DM562P-DS-P02
February 28, 2001
81-88
81-88
CA15 - CA8
O
Controller Address Bus
90-93,95-98
90-93,95-98
CA7 - CA0
O
Controller Address Bus
99-106
99-106
D7 - D0
I/O
Controller Data Bus
108
108
FR_SP2
I/O
Frame Signal Of Serial Port 2
109
109
FR_SP1
I/O
Frame Signal Of Serial Port 1
110
110
/POR
O
DSP Reset Output
111
112
111
112
VOICE Se1 1
VOICE Se1 2
O
Modem Control Output
Memory map is bit 1-2 of DAA at memory address
D000H
114
114
CODEC_CLK
O
20.16MHz Clock Output For DM6580 Chip
115
115
OSCO
O
Optional Codec X’tal clock output
116
116
OSCI
O
Optional Codec X’tal clock input
119
119
TD_SP2
O
Data Output Pin Of Serial Port 2
The serial data is clocked out through this pin
according to the rising edge of SCLK. The MSB is
sent immediately after the falling edge of the
FR_SP2 signal.
120
120
PS1
O
Modem Control Port Select Output:
Memory address mapping of the controller is
D800H.
122
122
EXT/INTB
I
Select Pin: Used to select internal or external
operation.
0: internal modem
1: external modem
7,14~17,26,
27,38~41,44,
53~56,64,65,
75,121,
124~127
NC
N
External only
PCI Interface ( pci internal only )
Pin No.
Pin Name
I/O
Description
78
POWEROFF
O
Power Off when high
121
INT#
O
PCI Interrupt Request
This signal will be asserted low when an interrupt condition as defined
in CR5 is set and the corresponding mask bit in CR7 is not set.
79
PCLK
I
PCI System Clock
This signal is the PCI bus clock that provides timing for all bus phases.
The frequency is 33MHz.
75
PME#
O
Power Management Event
The signal indicates that a power management event.
124~127,2~5
9~12,14~17
29~32,38~41
51~56,64,65
AD31~AD0
I/O
PCI Address & Data Bus
These are the multiplexed address and data signals.
DM6588 will decode each address on the bus and respond if it is the
target being addressed.
7IDSEL
I
Initialization Device Select
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