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VP4-0047-R 数据表(PDF) 8 Page - Eaton All Rights Reserved. |
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VP4-0047-R 数据表(HTML) 8 Page - Eaton All Rights Reserved. |
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8 / 9 page ![]() 8 VP VERSA-PAC® Inductors and Transformers (Surface Mount) 5V to 3.3V Buck Converter With 5V Output This circuit minimizes both board space and cost by eliminating a second regulator. VERSA-PAC’s gap serves to prevent core saturation during the switch on-time and also stores energy for the +5V load which is delivered during the flyback interval. The +3.3V buck winding is configured by placing two windings in series while the +5V is generated by an additional flyback winding stacked on the 3.3V output. Extra windings are paralleled with primary windings to handle more current. The turns ratio of 2:1 adds 1.67V to the +3.3V during the flyback interval to achieve +5V. +3.3V@ 12.5A +V RTN VERSA-PAC VP5-0083 12 11 10 9 8 7 1 2 3 4 5 6 Synchronous Controller IC + V + +5V@ 1A +3.3V@ 4.2A + RTN VERSA-PAC VP5-0083 LEVEL SHIFT 12,11 1,2 7 6 10,9,8 3,4,5 Synchronous Controller IC + 3.3V Buck Converter This circuit utilizes the gap of the VP5-0083 to handle the 12.5 Amp output current without saturating. In each of the five VERSA- PAC sizes, the gap is varied to achieve a selection of specific inductance and current values (see VERSA-PAC Data Table). All six windings are connected in parallel to minimize AC/DC copper losses and to maximize heat dissipation. With VERSA- PAC, this circuit works well at or above 300 KHz. Also, the closed flux-path EFD geometry enables much lower radiation characteristics than open-path bobbin core style components. LITHIUM-ION BATTERY TO 3.3V SEPIC CONVERTER The voltage of a Lithium-Ion Battery varies above and below +3.3V depending on the degree of charge. The SEPIC configuration takes advantage of VERSA-PAC’s multiple tightly coupled windings. This results in lower ripple current which lowers noise and core losses substantially. The circuit does not require a snubber to control the voltage “spike” associated with switch turn- off, and is quite efficient due to lower RMS current in the windings. +3.3V@ 6A VERSA-PAC VP5-0083 12 11 10 12 3 987 45 + + + 6 Controller IC W/Integral Switch 100 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 200 300 400 500 VP 5 VP 4 VP 3 VP 2 VP 1 Frequency, kHz 100 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 200 300 400 500 VP 5 VP 4 VP 3 VP 2 Bipolar (Push-Pull) Power vs Frequency Frequency, kHz Unipolar (Flyback) Power vs Frequency Technical Data 4301 Effective August 2017 VERSA-PAC® Performance characteristics VP 1 OCL vs. Isat 100.0% 90.0% 80.0% 70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% 140.0% 160.0% 180.0% 200.0% % of Isat These curves represent typical power handling capability. Indicated power levels may not be achievable with all configurations. Inductance characteristics www.eaton.com/electronics |
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