Advanced CMOS TTL Input – 74ACT32

Rev 1.0

10/05/19

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

FULL RANGE

4

UNITS

85°C

4.5V

0.1

0.1

0.1

5. All outputs loaded; thresholds on input associated with output under test. 6. Maximum test duration 2.0 ms, one output loaded at a time.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5.0V

9

10

10

Maximum Propagation

Delay, Input A or B to

Output Y (Figure 1)

5.0V

9

10

10

ns

5.5V

V

0.1

0.1

0.1

4.5V

0.36

0.44

0.44

Maximum Low-Level

Output Voltage

5.5V

5

0.36

0.44

0.44

V

Maximum Input

Leakage Current

5.5V

±0.1

±1.0

±1.0

µA

Additional Maximum

5.5V

1

1.5

1.5

mA

5.5V

-

75

75

Minimum Dynamic

mA

Output Current

6

5.5V

-

-75

-75

Maximum Quiescent

Supply Leakage

Current

5.5V

4

40

40

µA

PARAMETER

7. Not production tested in die form, characterized by chip design and tested in package.

SYMBOL

CONDITIONS

TYPICAL

UNITS

Maximum Input

Capacitance

5.0V

4.5

pF

Power Dissipation

Capacitance

5.0V

20

pF

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