9DB202CG

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 6, 2004

1

Integrated

Circuit

Systems, Inc.

ICS9DB202

The ICS9DB202 is a high perfromance 1-to-2 Dif-

ferential-to-HCSL Jitter Attenuator designed for use

in PCI Express™ systems. In some PCI Express™

systems, such as those found in desktop PCs, the

PCI Express™ clocks are generated from a low

bandwidth, high phase noise PLL frequency synthesizer. In these

systems, a jitter-attenuating device may be necessary in order

to reduce high frequency random and deterministic jitter com-

ponents from the PLL synthesizer and from the system board.

The ICS9DB202 has two PLL bandwidth modes. In low band-

width mode, the PLL loop bandwidth is 500kHz. This setting of-

fers the best jitter attenuation and is still high enough to pass a

triangular input spread spectrum profile. In high bandwidth mode,

the PLL bandwidth is at 1MHz and allows the PLL to pass more

spread spectrum modulation.

For serdes which have x10 reference multipliers instead of x12.5

multipliers, each of the two PCI Express™ outputs (PCIEX0:1)

can be set for 125MHz instead of 100MHz by configuring the

appropriate frequency select pins (FS0:1).

Features

• Two 0.7V current mode differential HCSL output pairs

• 1 differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 140MHz

• Output skew: 110ps (maximum)

• Cycle-to-cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package available

• Industrial temperature information available upon request

HiPerClockS™

ICS

nOE0

nCLK

CLK

BYPASS

nOE1

PCIEXT0

nPCIEXC0

PCIEXT1

nPCIEXC1

ICS9DB202

20-Lead TSSOP

6.50mm x 4.40mm x 0.92

package body

G Package

Top View

ICS9DB202

20-Lead, 209-MIL SSOP

5.30mm x 7.20mm x 1.75mm

body package

F Package

Top View

Phase

Detector

VCO

Loop

Filter

1 HiZ

0 Enabled

1 HiZ

0 Enabled

0 ÷4

1 ÷5

0 ÷5

1 ÷4

FS0

FS1

Internal Feedback

÷5

Current

Set

-

+

0

1

0

1

IREF

PLL_BW

CLK

nCLK

FS0

GND

PCIEXT0

PCIEXC0

nOE0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

BYPASS

IREF

FS1

GND

PCIEXT1

PCIEXC1

nOE1