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NT5CC64M16GP-DINA 数据表(PDF) 13 Page - Nanya Technology Corporation. |
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NT5CC64M16GP-DINA 数据表(HTML) 13 Page - Nanya Technology Corporation. |
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13 / 160 page  Version 2.2 13 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Reset and Initialization Sequence at Power- on Ramping (Cont’d) CK CK tCKSRX RESET CKE tIS ODT Command BA0-BA2 T=200us T=500us tXPR tMRD tMRD tMRD tMOD tZQinit. Do Not Care Time break 10ns MRS MRS MRS MRS ZQCL MR2 MR3 MR1 MR0 VDD, VDDQ * From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads. Te Tk NOP* NOP* Valid Valid Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW Td Tc Ta Tb Tf Tg Th Ti Tj tDLLK Valid Valid Reset Procedure at Stable Power (Cont’d) The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3 (L) SDRAM is ready for normal operation. Reset Procedure at Power Stable Condition CK CK tCKSRX RESET CKE tIS ODT Command BA0-BA2 T=100ns T=500us tXPR tMRD tMRD tMRD tMOD tZQinit. Do Not Care Time break 10ns MRS MRS MRS MRS ZQCL MR2 MR3 MR1 MR0 VDD, VDDQ * From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads. Te Tk NOP* NOP* Valid Valid Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW Td Tc Ta Tb Tf Tg Th Ti Tj tDLLK Valid Valid |
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