Selectable Lowpass/Bandpass Filter

Data Sheet

03/2001

Block Diagram________________

SCF

Section

Three

SCF

Section

One

4

Input

MUX

Filter

and

Clock

Select

(TYPE, FSEL, Fo)

SCF

Section

Two

Single

Pole

Lowpass

Buffer

Adjustable

Gain

IN1

IN2

IN3

IN4

G

Out

o

S1

S2

Input Selection

The input is selected using the Input Select Pins

S1 and S2.

S2

S1

Input

0

0

1

0

1

2

1

0

3

1

1

4

Digital Levels

All the clock and control pins (except TYPE and

G) are referenced between GND and VDD. In

single supply applications, the digital levels

should be CMOS levels from VSS to VDD. In dual

supply systems, the digital levels should be

CMOS levels from GND to VDD.

Ordering Information__________

Part Number

Package

Clock to Corner Ratio

50

50 or 100

50

50 or 100

100

100

50

50 or 100

50

50 or 100

100

100

MSFS1P

8 Pin DIP

MSFS2P

16 Pin DIP

MSFS3P

8 Pin DIP

MSFS4P

16 Pin DIP

MSFS5P

8 Pin DIP

MSFS6P

8 Pin DIP

MSFS1S

8 Pin SOIC

MSFS2S

16 Pin SOIC

MSFS3S

8 Pin SOIC

MSFS4S

16 Pin SOIC

MSFS5S

8 Pin SOIC

MSFS6S

8 Pin SOIC

Absolute Maximum Ratings

Power Supply Voltage

+6V

Storage Temperature

-60 to +150 C

Operating Temperature

0 to 70 C

Web Site “www.mix-sig.com”

© 2001 Mixed Signal Integration 8

Mixed Signal Integration Corporation reserves the right to change any product or specification without notice at any time. Mixed Signal Integration

products are not designed or authorized for use in life support systems. Mixed Signal Integration assumes no responsibility for errors in this docu-

ment.